1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device that includes a plurality of memory cells stacked vertically from a substrate and a fabrication method thereof.
2. Description of the Related Art
Non-volatile memory devices are memory devices that maintain data stored therein even when a power supply is interrupted. Currently, various non-volatile memory devices, for example, NAND-type flash memories, are widely used.
As an increase in the integration density of two-dimensional memory devices having single-layer memory cells formed on a silicon substrate may reach a limit, three-dimensional non-volatile memory devices having a plurality of memory cells stacked vertically on a silicon substrate may be implemented. Three-dimensional non-volatile memory devices include vertical channel-type devices having a plurality of word lines stacked along channels formed vertically to a substrate, and vertical gate-type devices having a plurality of channel layers deposited along gates formed vertically to a substrate.
Among these three-dimensional non-volatile memory devices, the channel layers of the vertical gate-type devices are deposited on the substrate with an insulating layer interposed there between, and thus the channel layers are connected to the substrate. This structure suggests that a portion functioning like a substrate body is not present in the three-dimensional non-volatile memory devices. Thus, in the three-dimensional non-volatile memory devices, an erase operation may not be performed by applying a high positive voltage to a substrate body having a high-concentration P-type impurity region to inject holes into a gate of the memory cell by Fowler-Nordheim Tunneling. Specifically, the erase operation in the three-dimensional non-volatile memory cell device is performed by applying a high voltage to the gate of a selection transistor of the three-dimensional non-volatile memory device to generate gate-induced drain leakage (GIDL) and supplying hot holes, which are produced by the GIDL current, to the channel.
However, the erase operation employing GIDL current is performed at low erase speed and efficiency and is difficult to achieve.
In addition, a non-volatile memory device comprises a plurality of strings, each including a source selection transistor, a memory cell transistor, and a drain selection transistor, which are connected to each other in series. A first end of the strings are connected to corresponding bit lines, and a second end of the strings are commonly connected to source lines.
However, as the number of strings, which are connected to source lines, increases, the resistance of the source lines due to an increase in current during a read operation is to be reduced.